Polished semiconductor wafer and process for producing it

ABSTRACT

A polished semiconductor wafer has a front surface and a back surface and an edge R, which is located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer. The maximum deviation of the flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 μm or less. A process for producing the semiconductor wafer, comprises at least one treatment of the semiconductor wafer with a liquid etchant and at least one polishing of at least a front surface of the semiconductor wafer, the etchant flowing onto a boundary of the semiconductor wafer during the treatment, and the boundary of the semiconductor wafer which faces the flow of etchant being at least partially shielded from being struck directly by the etchant. The shielding extends in the direction of a thickness d of the semiconductor wafer and is at least d+100 μm long.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates to a polished semiconductor wafer for thefabrication of electronic components, having a front surface and a backsurface and an edge which forms the periphery of the semiconductor waferand is part of a profiled boundary of the semiconductor wafer. Thesemiconductor wafer has a polished front surface, into which thecomponents are formed. Strict demands are imposed on the flatness of thefront surface, and these demands are extraordinarily high if it isintended to accommodate electronic structures with line widths of 0.1 μmor below (<0.1 μm technology). To enable the maximum number of circuitsof this type to be integrated, it is necessary to ensure the requiredflatness to as close as possible to the edge of the front surface.

[0003] 2. The Prior Art

[0004] Most efforts to increase the flatness of the side faces of thesemiconductor wafer in general and the front surface in particular haveconsistently been concentrated on substeps involved in the production ofa semiconductor wafer which influence the flatness. These substepsinclude in particular steps such as the lapping and/or grinding andpolishing of one or both side faces. At least one polishing step,carried out as a single-side or double-side polishing step, is virtuallyalways carried out. As is made clear by European Patent No. EP 1119031A2, however, it is also possible for substeps such as the etching of theside faces to have an effect on the flatness, in particular on theflatness in the edge region of the side faces. A semiconductor wafer isusually etched prior to a first polishing step, in order to removedamage from the surface left behind by a previous shaping operation, forexample by grinding and/or lapping of the semiconductor wafer. Theabovementioned patent application states that a raised portion in theedge region of the polished front surface of the semiconductor wafer islikely if the semiconductor wafer is exposed to a flow of a liquidetchant which is guided onto the boundary of the semiconductor waferduring etching. To avoid this effect, a shield can be positioned infront of the boundary of the semiconductor wafer preventing the etchantfrom being able to strike the boundary of the semiconductor waferdirectly. The document does not give any indications with regard to anypotential for targeted influencing of the flatness of a semiconductorwafer in its edge region, in particular with a view to making thesemiconductor wafer suitable for the ≦0.1 μm technology.

SUMMARY OF THE INVENTION

[0005] It is therefore an object of the present invention to demonstratesuch potential.

[0006] It has been found that the flatness that can be achieved bypolishing in the edge region of a semiconductor wafer can be influencedin a targeted fashion by prior etching of the semiconductor wafer. Thisis a surprising result, since hitherto it was assumed, even when usingthe process disclosed by EP 1119031 A2, that the semiconductor wafergeometry is adversely affected by the etching and that it will only bepossible to partially eliminate this adverse effect by optimizedpolishing.

[0007] The invention comprises a polished semiconductor wafer having afront surface and a back surface and an edge R, which is located at adistance of a radius from a center of the semiconductor wafer, forms aperiphery of the semiconductor wafer and is part of a profiled boundaryof the semiconductor wafer. A maximum deviation of the flatness of theback surface from an ideal plane in a range between R-6 mm and R-1 mm ofthe back surface is 0.7 μm or less.

[0008] This particular geometry of the back surface of the semiconductorwafer is an essential feature for making the semiconductor wafersuitable for the ≦0.1 μm technology. This result was likewiseunexpected, since the flatness of the front surface forms the focalpoint of interest with regard to possible minimum line widths ofelectronic structures. Furthermore, the inventors have established thatwhen producing a semiconductor wafer having this particular, it isessential for the etching step to be carried out in a certain way priorto a first polishing step.

[0009] The invention also includes a process for producing a polishedsemiconductor wafer, comprising at least one treatment of thesemiconductor wafer with a liquid etchant and at least one polishing ofat least a front surface of the semiconductor wafer, the etchant flowingonto a boundary of the semiconductor wafer during the treatment, and theboundary of the semiconductor wafer which faces the flow of etchantbeing at least partially shielded from being struck directly by theetchant. The boundary of the semiconductor wafer is shielded along adistance which extends in the direction of a thickness d of thesemiconductor wafer and is at least d+100 μm long.

[0010] Carrying out the etching step in this process results in asemiconductor wafer whose front surface and back surface areparticularly planar all the way to the edge region. The flatness of atleast the front surface is optimized during the subsequent polishing,with the improved flatness of the back surface being responsible forthis being possible, since the flatness of the front surface of asemiconductor wafer can scarcely be improved by a polishing step if theflatness of the back surface of the semiconductor wafer is relativelymoderate. It is essential to the invention for the boundary of thesemiconductor wafer which faces the flow of etchant to be at leastpartially shielded from the etchant flowing in. It is also essential forthe shielding action to cover a region before the boundary of thesemiconductor wafer which, as seen in a direction perpendicular to thedirection of flow of the etchant and parallel to the thickness of thesemiconductor wafer, is at least of a length which corresponds to thesum of the thickness of the semiconductor wafer and a length of 100 μm.

[0011] Therefore, the subject matter of the invention is also anarrangement comprising a semiconductor wafer and a shield which ispositioned in front of a boundary of the semiconductor wafer and atleast partially shields the boundary of the semiconductor wafer from aliquid etchant flowing onto the boundary. The boundary of thesemiconductor wafer has a profile which extends from an inner profileend E, over a length ρ, to an edge R of the semiconductor wafer. Theedge is located at a distance of a radius from a center of thesemiconductor wafer and forms a periphery of the semiconductor wafer.The shield has a border S which is closest to the boundary of thesemiconductor wafer and is at a distance Δ from the inner profile end Eand a border lying furthest from the boundary of the semiconductorwafer. The shield shielding the boundary of the semiconductor waferwhich faces the flow of etchant along a distance which extends in thedirection of a thickness d of the semiconductor wafer is at least d+100μm long.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Other objects and features of the present invention will becomeapparent from the following detailed description considered inconnection with the accompanying drawings. It is to be understood,however, that the drawings are designed as an illustration only and notas a definition of the limits of the invention.

[0013] In the drawings, wherein similar reference characters denotesimilar elements throughout the several views:

[0014]FIG. 1 shows a sectional view of a portion of a semiconductorwafer;

[0015]FIG. 2 diagrammatically depicts an edge region of thesemiconductor wafer and relates this region to an ideal plane;

[0016]FIG. 3 shows, in general form, the arrangement according to theinvention of the semiconductor wafer and the shield;

[0017]FIG. 4 uses a diagram based on a comparative example and threeexamples to demonstrate the effect of the invention on the flatness ofthe back surface of a semiconductor wafer in the edge region; and

[0018] FIGS. 5 to 12 show various embodiments of the arrangement of thesemiconductor wafer and the shield during the etching of thesemiconductor wafer; the arrangement shown in FIG. 5 forms part of theprior art.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0019]FIG. 1 shows the edge region of a silicon semiconductor wafer,since the invention has the effect of improving the flatness of thisregion. The semiconductor wafer 1 is illustrated in conjunction with atwo-dimensional system of coordinates, with the aid of which therelative position of the semiconductor wafer and the shield cansubsequently be clarified. The reference point for the system ofcoordinates is the center of the semiconductor wafer, which is rotatedabout this center during etching. The edge R of the semiconductor waferis located at a distance of a radius from the center and forms theperiphery of the semiconductor wafer. It is part of a profiled boundary4 of the semiconductor wafer, the profile being produced mechanicallyusing a shaping tool, for example a profile grinding wheel, in what isknown as an edge rounding step. The location of the profile which isclosest to the center is marked as the inner profile end E. The boundaryof the semiconductor wafer may be rounded symmetrically orasymmetrically. The edge region of the semiconductor wafer, which is ofparticular interest in connection with the invention, is located at adistance R-1 mm to R-6 mm from the center of the semiconductor wafer, onthe front surface 2 and the back surface 3 of the semiconductor wafer.

[0020] During the etching, the semiconductor wafer, which preferablysubstantially comprises silicon, is exposed to a flow of liquid etchantwhich flows to the boundary of the semiconductor wafer at a definedvelocity parallel to the radial direction shown in the system ofcoordinates. Suitable etchants are both alkaline and acid reactingsolutions. However, acid reacting solutions are preferred, since therisk that they will introduce metallic impurities into the semiconductormaterial is much lower. A particularly preferred etchant containsaqueous hydrogen fluoride solution and at least one oxidizing acid,particularly preferably nitric acid, and, if appropriate, furtheradditives. It is also particularly preferred for small gas bubbles to bedispersed in the etchant in order to make the removal of material byetching more uniform. This can be realized, for example, in accordancewith the description given in U.S. Pat. No. 5,451,267, the disclosure ofwhich is herein incorporated by reference.

[0021] The boundary of the semiconductor wafer which faces the flow ofetchant is to be at least partially shielded in the manner of theinvention. This means that at least part of the periphery of thesemiconductor wafer lying in the direction of flow of the etchant isshielded. The effect of the shielding on the flatness of the side facesof the semiconductor wafer is at its greatest, however, if the peripheryof the semiconductor wafer which lies in the direction of flow of theetchant is completely shielded in the manner of the invention. Thisoption is therefore also particularly preferred. On the other hand, itis also possible for the periphery of the semiconductor-wafer to bepartially or completely shielded in the manner of the invention beyondthe minimum requirement.

[0022] It can be seen from FIG. 2 that increased removal of material isregistered in the edge region of the semiconductor wafer 1, inparticular in the range from R-1 mm to R-4 mm. This results in a more orless pronounced deviation from an ideally planar surface, which it isintended to approach with a view to the flatness during the shaping ofthe front surface and the back surface as a model, in this region. Sincethis deviation can also only be eliminated to a limited extent bysubsequent polishing, it is desirable for this deviation after theetching step to be minimized.

[0023] This is achieved by the process according to the invention, ascan be seen from FIG. 3, by the boundary 4 of the semiconductor waferwhich faces the flow of etchant being shielded in a directionperpendicular to the direction of flow of the etchant along a distancewhich is at least d+100 μm long, where d denotes the thickness of thesemiconductor wafer. With regard to the system of coordinates shown,this means that the etchant, before it reaches the boundary of thesemiconductor wafer, is prevented from flowing onto the semiconductorwafer in the radial direction, with the obstacle in the verticaldirection of the system of coordinates existing at least over a lengthcorresponding to the sum of the thickness d of the semiconductor waferand a distance of 100 μm. To achieve this, a shield 5 is arranged infront of boundary 4 of the semiconductor wafer, for example in themanner presented in the above-mentioned EP 1119031 A2. However, unlikein this prior art, it should be noted that the shield must have athickness which satisfies the requirement that the flow of the etchantbe blocked over a length corresponding to the sum of the thickness d ofthe semiconductor wafer and a distance of 100 μm.

[0024] An arrangement of the semiconductor wafer and the shield which isin accordance with the general illustration shown in FIG. 3 isparticularly preferred. The thickness d of semiconductor wafer 1corresponds to the distance between front surface 2 and back surface 3of the semiconductor wafer. The profile extends from the inner profileend E over a length p to the edge R of the semiconductor wafer. Shield 5has a rear border located furthest from the boundary of thesemiconductor wafer and a border S located closest to the boundary ofthe semiconductor wafer. Border S is at a distance a, the size of whichis preferably 10 mm or less, from inner profile end E. In accordancewith the sectional illustration shown, the rear border may be straightor rounded with respect to the vertical direction of the system ofcoordinates. Furthermore, the body of shield 5 may have a rectangularperiphery, in accordance with the sectional illustration, with aconstant thickness t_(max), or, in accordance with the option indicatedby dashed lines, may be designed so as to taper toward one or bothborders. The degree of tapering may range between thickness t_(max) anda minimum thickness t_(min).

[0025] At border S, the shield may have a recess 6 which is formed inthe radial direction and extends down to a depth y to a base G of therecess. If this feature is present, it is particularly preferred for therelative position of the semiconductor wafer and the shield to beselected in such a way that the boundary of the semiconductor waferextends into the recess, for example even to such an extent that thedifference E-S becomes negative. The length of the shield, i.e. thedistance between the border S and the rear border, is preferably 5 to200 mm, particularly preferably 30 to 70 mm.

[0026] A semiconductor wafer which has been etched in accordance withthe invention is distinguished by the fact that its side faces areparticularly planar even in the edge region. This naturally also haspositive effects on the result of subsequent polishing of thesemiconductor wafer, since the flatness of the semiconductor wafer isimproved still further as a result. The subsequent polishing and anycleaning steps carried out before and after it are to be carried out inaccordance with the prior art. At least one polishing of at least thefront surface of the semiconductor wafer is carried out. The polishingcan be carried out as single-side polishing or as double-side polishing.In the case of single-side polishing of the front surface, the backsurface of the semiconductor wafer is fixed on a support plate, forexample by adhesive bonding. In the case of double-side polishing, thesemiconductor wafer lies in a freely moveable manner in a recess in acarrier. The high flatness of the back surface, even in its edge region,ensures that the polishing of the front surface produces a semiconductorwafer which is extremely planar on this surface all the way into theedge region. Such a successful polishing result can scarcely be achievedwith a semiconductor wafer which has been etched in accordance with theprior art and is less planar in the edge region of the side faces, sincethe locally reduced flatness in the edge region of the back surface istransferred to the front surface, where it also leads to deviations fromthe ideal plane.

[0027] If the front surface is polished a number of times, it isexpedient for the first polishing step to be carried out as stockremoval polishing and for the final polishing step to be carried out astouch polishing, these two varieties of polishing being distinguishedsubstantially by the amount of material removed during the polishing. Inthe case of touch polishing, the material removed is generally 2 μm orless and in the case of stock removal polishing, the material removedmay be up to 10 μm and above. In addition to the final polishing step,the semiconductor wafer can also be coated, for example by an epitaxiallayer being deposited on the front surface and/or by the back surfacebeing sealed with a layer of polycrystalline material and/or with anoxide layer.

[0028] A particularly preferred process sequence for production of theclaimed semiconductor wafer comprises the separation of thesemiconductor wafer by sawing a single crystal, the rounding of theboundary of the semiconductor wafer, if appropriate the grinding of thesemiconductor wafer, which may be carried out as single-side grinding orsequential or simultaneous double-side grinding, and/or the lapping,wet-chemical etching, if appropriate edge polishing, and polishing,which is carried out at least once, of the semiconductor wafer, cleaningsteps carried out between the processes and one or more coatingoperations which are carried out following the final polishing of a sideface.

COMPARATIVE EXAMPLE

[0029] A large number of silicon semiconductor wafers were sawn from asingle crystal with the aid of a wire saw, cleaned and subjected to edgerounding. Then, the semiconductor wafers were ground, lapped and etchedin groups, rotating, in a bath of an acidic etchant enriched with smallgas bubbles. The boundaries of the semiconductor wafers were in eachcase shielded by a shield which prevented the etchant from being able toflow directly onto the boundary. The arrangement of a semiconductorwafer and its shield is sketched in FIG. 5. In this Comparative Example,which forms part of the prior art, the shield had a rectangular crosssection with a thickness t_(max) which corresponded to the thickness dof the semiconductor wafer.

EXAMPLES 1 to 8

[0030] Other groups of semiconductor wafers of the same type as thoseused in the Comparative Example were etched under the same conditions,except that the shield used was designed in accordance with the generalembodiment shown in FIG. 3. The embodiments used specifically aresketched in FIGS. 6 to 12. The table given below summarizes theessential features of the arrangements used in the Comparative Exampleand in the Examples: TABLE 1 Shield Δ γ t_(max)-d t_(min)-d Taper-Taper- Round- (μm) (μm) (μm) (μm) ing a ing b ing Compara- 350 + ρ 0 0 0no no no tive example Example 1 350 + ρ 0 100 100 no no no Example 2350 + ρ 0 950 950 no no no Example 3 100 450 + ρ 1250 1250 no no noExample 4 0 350 + ρ 1250 1250 no no no Example 5 0 350 + ρ 1250 1250 nono yes Example 6 0 350 + ρ 1250 100 yes no no Example 7 0 350 + ρ 1250100 yes no yes Example 8 0 350 + ρ 1250 100 yes yes yes

[0031] Following the etching step, all of the groups of semiconductorwafers were cleaned and subjected to single-side polishing on the frontsurface. FIG. 4 compares the results of a test on the flatness of theback surface of the semiconductor wafers in the edge region for thesemiconductor wafers of the Comparative Example and of Examples 1 to 3in diagram form. It is clear that the semiconductor wafers which weretreated in accordance with the prior art did not achieve the criterionthat the maximum deviation of the flatness of the back surface from anideal plane in a range between R-6 mm and R-1 mm of the back surface be0.7 μm or less.

[0032] The table given below provides information on measurements(capacitive measuring method, ADE9900, E+ mode) of the local flatness ofthe semiconductor wafers of the Comparative Example and of Examples 1, 2and 3, expressed as SFQR 95%. The grid on which the measurements werebased comprised squares (sites) with an area of 22 mm×22 mm, and theedge exclusion was 1 mm. The data show that when the process accordingto the invention is used, it is possible to count on a significantlyimproved yield of particularly planar semiconductor wafers.Semiconductor wafers of this type are optimally suited to use in the<0.1 μm technology. TABLE 2 Comparative example example example Example1 2 3 SFQR 95% (μm) 1.91 1.35 1.05 0.62 After etching SFQR 95% (μm) 0.820.65 0.47 0.26 After polishing

[0033] Accordingly, while only a few embodiments of the presentinvention have been shown and described, it is obvious that many changesand modifications may be made thereunto without departing from thespirit and scope of the invention.

What is claimed is:
 1. A polished semiconductor wafer having a front surface and a back surface and an edge R, said edge R being located at a distance of a radius from a center of the semiconductor wafer, forms a periphery of the semiconductor wafer and is part of a profiled boundary of the semiconductor wafer, wherein a maximum deviation of flatness of the back surface from an ideal plane in a range between R-6 mm and R-1 mm of the back surface is 0.7 μm or less.
 2. The semiconductor wafer as claimed in claim 1, wherein the maximum deviation of the flatness of the back surface from the ideal plane in the range between R-6 mm and R-1 mm of the back surface is 0.5 μm or less.
 3. The semiconductor wafer as claimed in claim 1, wherein the front surface is formed by an epitaxially deposited layer.
 4. A process for producing a polished semiconductor wafer, comprising: treating the semiconductor wafer with a liquid etchant at least once, the etchant flowing onto a boundary of the semiconductor wafer during the step of treating; and polishing at least a front surface of the semiconductor wafer at least once; wherein the boundary of the semiconductor wafer which faces the flow of etchant is at least partially shielded from being struck directly by the etchant, and wherein the boundary of the semiconductor wafer is shielded along a distance which extends in a direction of a thickness d of the semiconductor wafer and is at least d+100 μm long.
 5. An arrangement comprising a semiconductor wafer and a shield which is positioned in front of a boundary of the semiconductor wafer and at least partially shields the boundary of the semiconductor wafer from a liquid etchant flowing onto the boundary, the arrangement having the following features: (1) the boundary of the semiconductor wafer is provided with a profile which extends from an inner profile end E, over a length p, to an edge R of the semiconductor wafer, (2) the edge is located at a distance of a radius from a center of the semiconductor wafer and forms a periphery of the semiconductor wafer, (3) the shield has a border S which is closest to the boundary of the semiconductor wafer and is at a distance A from the inner profile end E and a border lying furthest from the boundary of the semiconductor wafer, and (4) the shield shielding the boundary of the semiconductor wafer which faces the flow of etchant along a distance which extends in a direction of a thickness d of the semiconductor wafer is at least d+100 μm long.
 6. The arrangement as claimed in claim 5, wherein the distance A is at most 10 mm.
 7. The arrangement as claimed in claim 5, wherein the border S has a recess which extends down to a depth γ to a base G of the recess, and the boundary of the semiconductor wafer extends into the recess.
 8. The arrangement as claimed in claim 5, wherein the border of the shield which is furthest from the boundary of the semiconductor wafer is rounded.
 9. The arrangement as claimed in claim 5, wherein the shield has a body which is tapered toward at least one of the borders of the shield. 